For over a decade, SRAMs have been used in a variety of applications, especially low power applications and small system applications where the higher cost of such devices (e.g., as compared to DRAMs) is offset by simpler and less expensive system design. To date however, system designers have been forced to choose between using asynchronous SRAMs and synchronous SRAMs. Thus, circuit board layouts (e.g., pin out patterns) have been unique for synchronous SRAMs and asynchronous SRAMs.
FIG. 1 illustrates the main features of a synchronous SRAM 10. As shown, various inputs to the device are provided to associated input registers, which operate under the control of a common clock signal (e.g., a system clock signal provided to other components in the system within which the memory is located) and/or a control signal (not shown). For example, signals from an address bus 12 are usually latched in address registers 14. Likewise, data signals from a data bus 16 are latched in data registers 18. Some synchronous SRAMs also latch a read/write control signal 20 in a write enable register 22. Usually, the input registers 14, 18 and 22 operate under the control of an internal clock signal 24, provided by clock input circuitry 26, which receives the system clock (Clk) 28.
Address signals 30 from the address registers 14 are usually provided to row decoders 32 and column decoders 34. Often, the column decoders are associated with input/output (I/O circuitry (e.g., sense amplifiers and associated drivers) to access memory cells in the memory array 36. During a write, data signals 38 from the data registers 18 are provided to the column I/O circuits 34 through buffers 40 that are operated under the control of an internal write pulse 42. The internal write pulse 42 is usually generated by a combination of internal signals, for example the internal clock signal 24 and an internal write signal 44 from the write enable register 22. For a read, data signals 46 are provided from the I/O circuits 34 to output registers and buffers 48 that operate under the control of the internal clock signal 24 and an output signal 50. The output signal 50 is usually provided by an output enable buffer 52, which is used to receive the output enable signal 54 provided to the memory device (e.g., from a microprocessor or other memory control device). The output buffers 48 drive an output data bus 56.
Conventional synchronous SRAMs may also include burst control circuitry 58, which is used when burst operations are performed. During burst operations, multiple words may be read from the memory device 10, even though only a single address input is provided on the address bus 12. This is usually accomplished by providing a control signal (not shown) that indicates a burst operation is to be performed, along with the starting address for the operation. Data from that address is read out, followed by additional reads from other addresses. The information needed to generate the other addresses is provided to the row and column decoders by the burst control circuitry 58, which usually increments the starting address by some fixed value or values to generate the subsequent address information. The value(s) of the subsequent address(es) may depend on the type of burst operation being implemented, for example a linear sequential burst or an interleaved burst.
One important difference between synchronous SRAMs and asynchronous SRAMs is the use of a clock signal (Clk) to control the operations within the memory device. While the synchronous SRAM relies on such a signal, as shown in FIG. 2, the asynchronous SRAM does not. Instead, asynchronous SRAMs, such as asynchronous SRAM 100, operate independently of a system clock. Thus, address signals 102 from an address bus 102 are provided directly to row and column decoders 104 and 106. Again, the column decoders 106 may be associated with I/O circuitry (sense amplifiers and drivers, etc.) to allow for read and write operations. Thus, signals from a data bus 108 and a control bus 110 may be provided to the I/O circuits 106 to control these read and write operations. During a read, data signal from the array 112 are provided through the I/O circuitry 106 to output buffers 114, which also may be operated under the control of signals from the control bus 110, to ultimately provide data out signals 116. For a write, data signals from the data bus 108 are driven to memory cells of the array 106 specified by the address signals on address bus 102, through the I/O circuits 106.
Because the asynchronous SRAM 100 does not operate under the control of a system clock, designers must take care to ensure that any devices reading from and/or writing to the memory operate with compatible bus cycles. Further, because conventional asynchronous SRAMs typically do not operate in a burst mode, each read operation must typically be associated with a separate read address provided on address bus 102.
Synchronous and asynchronous SRAMs each have associated benefits and drawbacks, making each type of device better suited to some applications than others. For example, high performance systems that require memories to operate without skews often require the use of synchronous SRAMs. However, to date no single SRAM device (i.e., no single integrated circuit) has offered the option of choosing a synchronous or asynchronous mode of operation.